mirror of
https://github.com/golang/go.git
synced 2026-02-03 09:25:06 +03:00
[dev.simd] cmd/compile: add ShiftAll immediate variant
This CL is generated by CL 693136. Change-Id: Ifd2278d3f927efa008a14cc5e592e7c14b7120ff Reviewed-on: https://go-review.googlesource.com/c/go/+/693157 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: David Chase <drchase@google.com>
This commit is contained in:
Junyang Shao
@@ -689,7 +689,34 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
|
||||
ssa.OpAMD64VPRORD512,
|
||||
ssa.OpAMD64VPRORQ128,
|
||||
ssa.OpAMD64VPRORQ256,
|
||||
ssa.OpAMD64VPRORQ512:
|
||||
ssa.OpAMD64VPRORQ512,
|
||||
ssa.OpAMD64VPSLLW128const,
|
||||
ssa.OpAMD64VPSLLW256const,
|
||||
ssa.OpAMD64VPSLLW512const,
|
||||
ssa.OpAMD64VPSLLD128const,
|
||||
ssa.OpAMD64VPSLLD256const,
|
||||
ssa.OpAMD64VPSLLD512const,
|
||||
ssa.OpAMD64VPSLLQ128const,
|
||||
ssa.OpAMD64VPSLLQ256const,
|
||||
ssa.OpAMD64VPSLLQ512const,
|
||||
ssa.OpAMD64VPSRLW128const,
|
||||
ssa.OpAMD64VPSRLW256const,
|
||||
ssa.OpAMD64VPSRLW512const,
|
||||
ssa.OpAMD64VPSRLD128const,
|
||||
ssa.OpAMD64VPSRLD256const,
|
||||
ssa.OpAMD64VPSRLD512const,
|
||||
ssa.OpAMD64VPSRLQ128const,
|
||||
ssa.OpAMD64VPSRLQ256const,
|
||||
ssa.OpAMD64VPSRLQ512const,
|
||||
ssa.OpAMD64VPSRAW128const,
|
||||
ssa.OpAMD64VPSRAW256const,
|
||||
ssa.OpAMD64VPSRAW512const,
|
||||
ssa.OpAMD64VPSRAD128const,
|
||||
ssa.OpAMD64VPSRAD256const,
|
||||
ssa.OpAMD64VPSRAD512const,
|
||||
ssa.OpAMD64VPSRAQ128const,
|
||||
ssa.OpAMD64VPSRAQ256const,
|
||||
ssa.OpAMD64VPSRAQ512const:
|
||||
p = simdV11Imm8(s, v)
|
||||
|
||||
case ssa.OpAMD64VRNDSCALEPSMasked128,
|
||||
@@ -715,7 +742,34 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
|
||||
ssa.OpAMD64VPRORDMasked512,
|
||||
ssa.OpAMD64VPRORQMasked128,
|
||||
ssa.OpAMD64VPRORQMasked256,
|
||||
ssa.OpAMD64VPRORQMasked512:
|
||||
ssa.OpAMD64VPRORQMasked512,
|
||||
ssa.OpAMD64VPSLLWMasked128const,
|
||||
ssa.OpAMD64VPSLLWMasked256const,
|
||||
ssa.OpAMD64VPSLLWMasked512const,
|
||||
ssa.OpAMD64VPSLLDMasked128const,
|
||||
ssa.OpAMD64VPSLLDMasked256const,
|
||||
ssa.OpAMD64VPSLLDMasked512const,
|
||||
ssa.OpAMD64VPSLLQMasked128const,
|
||||
ssa.OpAMD64VPSLLQMasked256const,
|
||||
ssa.OpAMD64VPSLLQMasked512const,
|
||||
ssa.OpAMD64VPSRLWMasked128const,
|
||||
ssa.OpAMD64VPSRLWMasked256const,
|
||||
ssa.OpAMD64VPSRLWMasked512const,
|
||||
ssa.OpAMD64VPSRLDMasked128const,
|
||||
ssa.OpAMD64VPSRLDMasked256const,
|
||||
ssa.OpAMD64VPSRLDMasked512const,
|
||||
ssa.OpAMD64VPSRLQMasked128const,
|
||||
ssa.OpAMD64VPSRLQMasked256const,
|
||||
ssa.OpAMD64VPSRLQMasked512const,
|
||||
ssa.OpAMD64VPSRAWMasked128const,
|
||||
ssa.OpAMD64VPSRAWMasked256const,
|
||||
ssa.OpAMD64VPSRAWMasked512const,
|
||||
ssa.OpAMD64VPSRADMasked128const,
|
||||
ssa.OpAMD64VPSRADMasked256const,
|
||||
ssa.OpAMD64VPSRADMasked512const,
|
||||
ssa.OpAMD64VPSRAQMasked128const,
|
||||
ssa.OpAMD64VPSRAQMasked256const,
|
||||
ssa.OpAMD64VPSRAQMasked512const:
|
||||
p = simdVkvImm8(s, v)
|
||||
|
||||
case ssa.OpAMD64VDPPS128,
|
||||
@@ -1497,7 +1551,34 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
|
||||
ssa.OpAMD64VPXORDMasked512,
|
||||
ssa.OpAMD64VPXORQMasked128,
|
||||
ssa.OpAMD64VPXORQMasked256,
|
||||
ssa.OpAMD64VPXORQMasked512:
|
||||
ssa.OpAMD64VPXORQMasked512,
|
||||
ssa.OpAMD64VPSLLWMasked128const,
|
||||
ssa.OpAMD64VPSLLWMasked256const,
|
||||
ssa.OpAMD64VPSLLWMasked512const,
|
||||
ssa.OpAMD64VPSLLDMasked128const,
|
||||
ssa.OpAMD64VPSLLDMasked256const,
|
||||
ssa.OpAMD64VPSLLDMasked512const,
|
||||
ssa.OpAMD64VPSLLQMasked128const,
|
||||
ssa.OpAMD64VPSLLQMasked256const,
|
||||
ssa.OpAMD64VPSLLQMasked512const,
|
||||
ssa.OpAMD64VPSRLWMasked128const,
|
||||
ssa.OpAMD64VPSRLWMasked256const,
|
||||
ssa.OpAMD64VPSRLWMasked512const,
|
||||
ssa.OpAMD64VPSRLDMasked128const,
|
||||
ssa.OpAMD64VPSRLDMasked256const,
|
||||
ssa.OpAMD64VPSRLDMasked512const,
|
||||
ssa.OpAMD64VPSRLQMasked128const,
|
||||
ssa.OpAMD64VPSRLQMasked256const,
|
||||
ssa.OpAMD64VPSRLQMasked512const,
|
||||
ssa.OpAMD64VPSRAWMasked128const,
|
||||
ssa.OpAMD64VPSRAWMasked256const,
|
||||
ssa.OpAMD64VPSRAWMasked512const,
|
||||
ssa.OpAMD64VPSRADMasked128const,
|
||||
ssa.OpAMD64VPSRADMasked256const,
|
||||
ssa.OpAMD64VPSRADMasked512const,
|
||||
ssa.OpAMD64VPSRAQMasked128const,
|
||||
ssa.OpAMD64VPSRAQMasked256const,
|
||||
ssa.OpAMD64VPSRAQMasked512const:
|
||||
x86.ParseSuffix(p, "Z")
|
||||
}
|
||||
|
||||
|
||||
@@ -1345,24 +1345,42 @@
|
||||
(SetElemUint16x8 ...) => (VPINSRW128 ...)
|
||||
(SetElemUint32x4 ...) => (VPINSRD128 ...)
|
||||
(SetElemUint64x2 ...) => (VPINSRQ128 ...)
|
||||
(ShiftAllLeftInt16x8 ...) => (VPSLLW128 ...)
|
||||
(ShiftAllLeftInt16x16 ...) => (VPSLLW256 ...)
|
||||
(ShiftAllLeftInt16x32 ...) => (VPSLLW512 ...)
|
||||
(ShiftAllLeftInt32x4 ...) => (VPSLLD128 ...)
|
||||
(ShiftAllLeftInt32x8 ...) => (VPSLLD256 ...)
|
||||
(ShiftAllLeftInt32x16 ...) => (VPSLLD512 ...)
|
||||
(ShiftAllLeftInt64x2 ...) => (VPSLLQ128 ...)
|
||||
(ShiftAllLeftInt64x4 ...) => (VPSLLQ256 ...)
|
||||
(ShiftAllLeftInt64x8 ...) => (VPSLLQ512 ...)
|
||||
(ShiftAllLeftUint16x8 ...) => (VPSLLW128 ...)
|
||||
(ShiftAllLeftUint16x16 ...) => (VPSLLW256 ...)
|
||||
(ShiftAllLeftUint16x32 ...) => (VPSLLW512 ...)
|
||||
(ShiftAllLeftUint32x4 ...) => (VPSLLD128 ...)
|
||||
(ShiftAllLeftUint32x8 ...) => (VPSLLD256 ...)
|
||||
(ShiftAllLeftUint32x16 ...) => (VPSLLD512 ...)
|
||||
(ShiftAllLeftUint64x2 ...) => (VPSLLQ128 ...)
|
||||
(ShiftAllLeftUint64x4 ...) => (VPSLLQ256 ...)
|
||||
(ShiftAllLeftUint64x8 ...) => (VPSLLQ512 ...)
|
||||
(ShiftAllLeftInt16x8 x (MOVQconst [c])) => (VPSLLW128const [int8(c)] x)
|
||||
(ShiftAllLeftInt16x8 x y) => (VPSLLW128 x y)
|
||||
(ShiftAllLeftInt16x16 x (MOVQconst [c])) => (VPSLLW256const [int8(c)] x)
|
||||
(ShiftAllLeftInt16x16 x y) => (VPSLLW256 x y)
|
||||
(ShiftAllLeftInt16x32 x (MOVQconst [c])) => (VPSLLW512const [int8(c)] x)
|
||||
(ShiftAllLeftInt16x32 x y) => (VPSLLW512 x y)
|
||||
(ShiftAllLeftInt32x4 x (MOVQconst [c])) => (VPSLLD128const [int8(c)] x)
|
||||
(ShiftAllLeftInt32x4 x y) => (VPSLLD128 x y)
|
||||
(ShiftAllLeftInt32x8 x (MOVQconst [c])) => (VPSLLD256const [int8(c)] x)
|
||||
(ShiftAllLeftInt32x8 x y) => (VPSLLD256 x y)
|
||||
(ShiftAllLeftInt32x16 x (MOVQconst [c])) => (VPSLLD512const [int8(c)] x)
|
||||
(ShiftAllLeftInt32x16 x y) => (VPSLLD512 x y)
|
||||
(ShiftAllLeftInt64x2 x (MOVQconst [c])) => (VPSLLQ128const [int8(c)] x)
|
||||
(ShiftAllLeftInt64x2 x y) => (VPSLLQ128 x y)
|
||||
(ShiftAllLeftInt64x4 x (MOVQconst [c])) => (VPSLLQ256const [int8(c)] x)
|
||||
(ShiftAllLeftInt64x4 x y) => (VPSLLQ256 x y)
|
||||
(ShiftAllLeftInt64x8 x (MOVQconst [c])) => (VPSLLQ512const [int8(c)] x)
|
||||
(ShiftAllLeftInt64x8 x y) => (VPSLLQ512 x y)
|
||||
(ShiftAllLeftUint16x8 x (MOVQconst [c])) => (VPSLLW128const [int8(c)] x)
|
||||
(ShiftAllLeftUint16x8 x y) => (VPSLLW128 x y)
|
||||
(ShiftAllLeftUint16x16 x (MOVQconst [c])) => (VPSLLW256const [int8(c)] x)
|
||||
(ShiftAllLeftUint16x16 x y) => (VPSLLW256 x y)
|
||||
(ShiftAllLeftUint16x32 x (MOVQconst [c])) => (VPSLLW512const [int8(c)] x)
|
||||
(ShiftAllLeftUint16x32 x y) => (VPSLLW512 x y)
|
||||
(ShiftAllLeftUint32x4 x (MOVQconst [c])) => (VPSLLD128const [int8(c)] x)
|
||||
(ShiftAllLeftUint32x4 x y) => (VPSLLD128 x y)
|
||||
(ShiftAllLeftUint32x8 x (MOVQconst [c])) => (VPSLLD256const [int8(c)] x)
|
||||
(ShiftAllLeftUint32x8 x y) => (VPSLLD256 x y)
|
||||
(ShiftAllLeftUint32x16 x (MOVQconst [c])) => (VPSLLD512const [int8(c)] x)
|
||||
(ShiftAllLeftUint32x16 x y) => (VPSLLD512 x y)
|
||||
(ShiftAllLeftUint64x2 x (MOVQconst [c])) => (VPSLLQ128const [int8(c)] x)
|
||||
(ShiftAllLeftUint64x2 x y) => (VPSLLQ128 x y)
|
||||
(ShiftAllLeftUint64x4 x (MOVQconst [c])) => (VPSLLQ256const [int8(c)] x)
|
||||
(ShiftAllLeftUint64x4 x y) => (VPSLLQ256 x y)
|
||||
(ShiftAllLeftUint64x8 x (MOVQconst [c])) => (VPSLLQ512const [int8(c)] x)
|
||||
(ShiftAllLeftUint64x8 x y) => (VPSLLQ512 x y)
|
||||
(ShiftAllLeftConcatInt16x8 ...) => (VPSHLDW128 ...)
|
||||
(ShiftAllLeftConcatInt16x16 ...) => (VPSHLDW256 ...)
|
||||
(ShiftAllLeftConcatInt16x32 ...) => (VPSHLDW512 ...)
|
||||
@@ -1399,42 +1417,78 @@
|
||||
(ShiftAllLeftConcatMaskedUint64x2 [a] x y mask) => (VPSHLDQMasked128 [a] x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftConcatMaskedUint64x4 [a] x y mask) => (VPSHLDQMasked256 [a] x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftConcatMaskedUint64x8 [a] x y mask) => (VPSHLDQMasked512 [a] x y (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedInt16x8 x (MOVQconst [c]) mask) => (VPSLLWMasked128const [int8(c)] x (VPMOVVec16x8ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedInt16x8 x y mask) => (VPSLLWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedInt16x16 x (MOVQconst [c]) mask) => (VPSLLWMasked256const [int8(c)] x (VPMOVVec16x16ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedInt16x16 x y mask) => (VPSLLWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedInt16x32 x (MOVQconst [c]) mask) => (VPSLLWMasked512const [int8(c)] x (VPMOVVec16x32ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedInt16x32 x y mask) => (VPSLLWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedInt32x4 x (MOVQconst [c]) mask) => (VPSLLDMasked128const [int8(c)] x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedInt32x4 x y mask) => (VPSLLDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedInt32x8 x (MOVQconst [c]) mask) => (VPSLLDMasked256const [int8(c)] x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedInt32x8 x y mask) => (VPSLLDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedInt32x16 x (MOVQconst [c]) mask) => (VPSLLDMasked512const [int8(c)] x (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedInt32x16 x y mask) => (VPSLLDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedInt64x2 x (MOVQconst [c]) mask) => (VPSLLQMasked128const [int8(c)] x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedInt64x2 x y mask) => (VPSLLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedInt64x4 x (MOVQconst [c]) mask) => (VPSLLQMasked256const [int8(c)] x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedInt64x4 x y mask) => (VPSLLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedInt64x8 x (MOVQconst [c]) mask) => (VPSLLQMasked512const [int8(c)] x (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedInt64x8 x y mask) => (VPSLLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedUint16x8 x (MOVQconst [c]) mask) => (VPSLLWMasked128const [int8(c)] x (VPMOVVec16x8ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedUint16x8 x y mask) => (VPSLLWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedUint16x16 x (MOVQconst [c]) mask) => (VPSLLWMasked256const [int8(c)] x (VPMOVVec16x16ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedUint16x16 x y mask) => (VPSLLWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedUint16x32 x (MOVQconst [c]) mask) => (VPSLLWMasked512const [int8(c)] x (VPMOVVec16x32ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedUint16x32 x y mask) => (VPSLLWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedUint32x4 x (MOVQconst [c]) mask) => (VPSLLDMasked128const [int8(c)] x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedUint32x4 x y mask) => (VPSLLDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedUint32x8 x (MOVQconst [c]) mask) => (VPSLLDMasked256const [int8(c)] x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedUint32x8 x y mask) => (VPSLLDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedUint32x16 x (MOVQconst [c]) mask) => (VPSLLDMasked512const [int8(c)] x (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedUint32x16 x y mask) => (VPSLLDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedUint64x2 x (MOVQconst [c]) mask) => (VPSLLQMasked128const [int8(c)] x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedUint64x2 x y mask) => (VPSLLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedUint64x4 x (MOVQconst [c]) mask) => (VPSLLQMasked256const [int8(c)] x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedUint64x4 x y mask) => (VPSLLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedUint64x8 x (MOVQconst [c]) mask) => (VPSLLQMasked512const [int8(c)] x (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(ShiftAllLeftMaskedUint64x8 x y mask) => (VPSLLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightInt16x8 ...) => (VPSRAW128 ...)
|
||||
(ShiftAllRightInt16x16 ...) => (VPSRAW256 ...)
|
||||
(ShiftAllRightInt16x32 ...) => (VPSRAW512 ...)
|
||||
(ShiftAllRightInt32x4 ...) => (VPSRAD128 ...)
|
||||
(ShiftAllRightInt32x8 ...) => (VPSRAD256 ...)
|
||||
(ShiftAllRightInt32x16 ...) => (VPSRAD512 ...)
|
||||
(ShiftAllRightInt64x2 ...) => (VPSRAQ128 ...)
|
||||
(ShiftAllRightInt64x4 ...) => (VPSRAQ256 ...)
|
||||
(ShiftAllRightInt64x8 ...) => (VPSRAQ512 ...)
|
||||
(ShiftAllRightUint16x8 ...) => (VPSRLW128 ...)
|
||||
(ShiftAllRightUint16x16 ...) => (VPSRLW256 ...)
|
||||
(ShiftAllRightUint16x32 ...) => (VPSRLW512 ...)
|
||||
(ShiftAllRightUint32x4 ...) => (VPSRLD128 ...)
|
||||
(ShiftAllRightUint32x8 ...) => (VPSRLD256 ...)
|
||||
(ShiftAllRightUint32x16 ...) => (VPSRLD512 ...)
|
||||
(ShiftAllRightUint64x2 ...) => (VPSRLQ128 ...)
|
||||
(ShiftAllRightUint64x4 ...) => (VPSRLQ256 ...)
|
||||
(ShiftAllRightUint64x8 ...) => (VPSRLQ512 ...)
|
||||
(ShiftAllRightInt16x8 x (MOVQconst [c])) => (VPSRAW128const [int8(c)] x)
|
||||
(ShiftAllRightInt16x8 x y) => (VPSRAW128 x y)
|
||||
(ShiftAllRightInt16x16 x (MOVQconst [c])) => (VPSRAW256const [int8(c)] x)
|
||||
(ShiftAllRightInt16x16 x y) => (VPSRAW256 x y)
|
||||
(ShiftAllRightInt16x32 x (MOVQconst [c])) => (VPSRAW512const [int8(c)] x)
|
||||
(ShiftAllRightInt16x32 x y) => (VPSRAW512 x y)
|
||||
(ShiftAllRightInt32x4 x (MOVQconst [c])) => (VPSRAD128const [int8(c)] x)
|
||||
(ShiftAllRightInt32x4 x y) => (VPSRAD128 x y)
|
||||
(ShiftAllRightInt32x8 x (MOVQconst [c])) => (VPSRAD256const [int8(c)] x)
|
||||
(ShiftAllRightInt32x8 x y) => (VPSRAD256 x y)
|
||||
(ShiftAllRightInt32x16 x (MOVQconst [c])) => (VPSRAD512const [int8(c)] x)
|
||||
(ShiftAllRightInt32x16 x y) => (VPSRAD512 x y)
|
||||
(ShiftAllRightInt64x2 x (MOVQconst [c])) => (VPSRAQ128const [int8(c)] x)
|
||||
(ShiftAllRightInt64x2 x y) => (VPSRAQ128 x y)
|
||||
(ShiftAllRightInt64x4 x (MOVQconst [c])) => (VPSRAQ256const [int8(c)] x)
|
||||
(ShiftAllRightInt64x4 x y) => (VPSRAQ256 x y)
|
||||
(ShiftAllRightInt64x8 x (MOVQconst [c])) => (VPSRAQ512const [int8(c)] x)
|
||||
(ShiftAllRightInt64x8 x y) => (VPSRAQ512 x y)
|
||||
(ShiftAllRightUint16x8 x (MOVQconst [c])) => (VPSRLW128const [int8(c)] x)
|
||||
(ShiftAllRightUint16x8 x y) => (VPSRLW128 x y)
|
||||
(ShiftAllRightUint16x16 x (MOVQconst [c])) => (VPSRLW256const [int8(c)] x)
|
||||
(ShiftAllRightUint16x16 x y) => (VPSRLW256 x y)
|
||||
(ShiftAllRightUint16x32 x (MOVQconst [c])) => (VPSRLW512const [int8(c)] x)
|
||||
(ShiftAllRightUint16x32 x y) => (VPSRLW512 x y)
|
||||
(ShiftAllRightUint32x4 x (MOVQconst [c])) => (VPSRLD128const [int8(c)] x)
|
||||
(ShiftAllRightUint32x4 x y) => (VPSRLD128 x y)
|
||||
(ShiftAllRightUint32x8 x (MOVQconst [c])) => (VPSRLD256const [int8(c)] x)
|
||||
(ShiftAllRightUint32x8 x y) => (VPSRLD256 x y)
|
||||
(ShiftAllRightUint32x16 x (MOVQconst [c])) => (VPSRLD512const [int8(c)] x)
|
||||
(ShiftAllRightUint32x16 x y) => (VPSRLD512 x y)
|
||||
(ShiftAllRightUint64x2 x (MOVQconst [c])) => (VPSRLQ128const [int8(c)] x)
|
||||
(ShiftAllRightUint64x2 x y) => (VPSRLQ128 x y)
|
||||
(ShiftAllRightUint64x4 x (MOVQconst [c])) => (VPSRLQ256const [int8(c)] x)
|
||||
(ShiftAllRightUint64x4 x y) => (VPSRLQ256 x y)
|
||||
(ShiftAllRightUint64x8 x (MOVQconst [c])) => (VPSRLQ512const [int8(c)] x)
|
||||
(ShiftAllRightUint64x8 x y) => (VPSRLQ512 x y)
|
||||
(ShiftAllRightConcatInt16x8 ...) => (VPSHRDW128 ...)
|
||||
(ShiftAllRightConcatInt16x16 ...) => (VPSHRDW256 ...)
|
||||
(ShiftAllRightConcatInt16x32 ...) => (VPSHRDW512 ...)
|
||||
@@ -1471,23 +1525,41 @@
|
||||
(ShiftAllRightConcatMaskedUint64x2 [a] x y mask) => (VPSHRDQMasked128 [a] x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightConcatMaskedUint64x4 [a] x y mask) => (VPSHRDQMasked256 [a] x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightConcatMaskedUint64x8 [a] x y mask) => (VPSHRDQMasked512 [a] x y (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedInt16x8 x (MOVQconst [c]) mask) => (VPSRAWMasked128const [int8(c)] x (VPMOVVec16x8ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedInt16x8 x y mask) => (VPSRAWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedInt16x16 x (MOVQconst [c]) mask) => (VPSRAWMasked256const [int8(c)] x (VPMOVVec16x16ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedInt16x16 x y mask) => (VPSRAWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedInt16x32 x (MOVQconst [c]) mask) => (VPSRAWMasked512const [int8(c)] x (VPMOVVec16x32ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedInt16x32 x y mask) => (VPSRAWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedInt32x4 x (MOVQconst [c]) mask) => (VPSRADMasked128const [int8(c)] x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedInt32x4 x y mask) => (VPSRADMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedInt32x8 x (MOVQconst [c]) mask) => (VPSRADMasked256const [int8(c)] x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedInt32x8 x y mask) => (VPSRADMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedInt32x16 x (MOVQconst [c]) mask) => (VPSRADMasked512const [int8(c)] x (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedInt32x16 x y mask) => (VPSRADMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedInt64x2 x (MOVQconst [c]) mask) => (VPSRAQMasked128const [int8(c)] x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedInt64x2 x y mask) => (VPSRAQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedInt64x4 x (MOVQconst [c]) mask) => (VPSRAQMasked256const [int8(c)] x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedInt64x4 x y mask) => (VPSRAQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedInt64x8 x (MOVQconst [c]) mask) => (VPSRAQMasked512const [int8(c)] x (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedInt64x8 x y mask) => (VPSRAQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedUint16x8 x (MOVQconst [c]) mask) => (VPSRLWMasked128const [int8(c)] x (VPMOVVec16x8ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedUint16x8 x y mask) => (VPSRLWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedUint16x16 x (MOVQconst [c]) mask) => (VPSRLWMasked256const [int8(c)] x (VPMOVVec16x16ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedUint16x16 x y mask) => (VPSRLWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedUint16x32 x (MOVQconst [c]) mask) => (VPSRLWMasked512const [int8(c)] x (VPMOVVec16x32ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedUint16x32 x y mask) => (VPSRLWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedUint32x4 x (MOVQconst [c]) mask) => (VPSRLDMasked128const [int8(c)] x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedUint32x4 x y mask) => (VPSRLDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedUint32x8 x (MOVQconst [c]) mask) => (VPSRLDMasked256const [int8(c)] x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedUint32x8 x y mask) => (VPSRLDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedUint32x16 x (MOVQconst [c]) mask) => (VPSRLDMasked512const [int8(c)] x (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedUint32x16 x y mask) => (VPSRLDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedUint64x2 x (MOVQconst [c]) mask) => (VPSRLQMasked128const [int8(c)] x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedUint64x2 x y mask) => (VPSRLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedUint64x4 x (MOVQconst [c]) mask) => (VPSRLQMasked256const [int8(c)] x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedUint64x4 x y mask) => (VPSRLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedUint64x8 x (MOVQconst [c]) mask) => (VPSRLQMasked512const [int8(c)] x (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(ShiftAllRightMaskedUint64x8 x y mask) => (VPSRLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(ShiftLeftInt16x8 ...) => (VPSLLVW128 ...)
|
||||
(ShiftLeftInt16x16 ...) => (VPSLLVW256 ...)
|
||||
|
||||
@@ -1002,5 +1002,59 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf
|
||||
{name: "VPSHRDQMasked128", argLength: 3, reg: w2kw, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VPSHRDQMasked256", argLength: 3, reg: w2kw, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VPSHRDQMasked512", argLength: 3, reg: w2kw, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VPSLLW128const", argLength: 1, reg: v11, asm: "VPSLLW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VPSLLW256const", argLength: 1, reg: v11, asm: "VPSLLW", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VPSLLW512const", argLength: 1, reg: w11, asm: "VPSLLW", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VPSLLD128const", argLength: 1, reg: v11, asm: "VPSLLD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VPSLLD256const", argLength: 1, reg: v11, asm: "VPSLLD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VPSLLD512const", argLength: 1, reg: w11, asm: "VPSLLD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VPSLLQ128const", argLength: 1, reg: v11, asm: "VPSLLQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VPSLLQ256const", argLength: 1, reg: v11, asm: "VPSLLQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VPSLLQ512const", argLength: 1, reg: w11, asm: "VPSLLQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VPSLLWMasked128const", argLength: 2, reg: wkw, asm: "VPSLLW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VPSLLWMasked256const", argLength: 2, reg: wkw, asm: "VPSLLW", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VPSLLWMasked512const", argLength: 2, reg: wkw, asm: "VPSLLW", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VPSLLDMasked128const", argLength: 2, reg: wkw, asm: "VPSLLD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VPSLLDMasked256const", argLength: 2, reg: wkw, asm: "VPSLLD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VPSLLDMasked512const", argLength: 2, reg: wkw, asm: "VPSLLD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VPSLLQMasked128const", argLength: 2, reg: wkw, asm: "VPSLLQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VPSLLQMasked256const", argLength: 2, reg: wkw, asm: "VPSLLQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VPSLLQMasked512const", argLength: 2, reg: wkw, asm: "VPSLLQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VPSRLW128const", argLength: 1, reg: v11, asm: "VPSRLW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VPSRLW256const", argLength: 1, reg: v11, asm: "VPSRLW", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VPSRLW512const", argLength: 1, reg: w11, asm: "VPSRLW", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VPSRLD128const", argLength: 1, reg: v11, asm: "VPSRLD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VPSRLD256const", argLength: 1, reg: v11, asm: "VPSRLD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VPSRLD512const", argLength: 1, reg: w11, asm: "VPSRLD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VPSRLQ128const", argLength: 1, reg: v11, asm: "VPSRLQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VPSRLQ256const", argLength: 1, reg: v11, asm: "VPSRLQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VPSRLQ512const", argLength: 1, reg: w11, asm: "VPSRLQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VPSRAW128const", argLength: 1, reg: v11, asm: "VPSRAW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VPSRAW256const", argLength: 1, reg: v11, asm: "VPSRAW", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VPSRAW512const", argLength: 1, reg: w11, asm: "VPSRAW", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VPSRAD128const", argLength: 1, reg: v11, asm: "VPSRAD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VPSRAD256const", argLength: 1, reg: v11, asm: "VPSRAD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VPSRAD512const", argLength: 1, reg: w11, asm: "VPSRAD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VPSRAQ128const", argLength: 1, reg: w11, asm: "VPSRAQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VPSRAQ256const", argLength: 1, reg: w11, asm: "VPSRAQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VPSRAQ512const", argLength: 1, reg: w11, asm: "VPSRAQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VPSRLWMasked128const", argLength: 2, reg: wkw, asm: "VPSRLW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VPSRLWMasked256const", argLength: 2, reg: wkw, asm: "VPSRLW", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VPSRLWMasked512const", argLength: 2, reg: wkw, asm: "VPSRLW", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VPSRLDMasked128const", argLength: 2, reg: wkw, asm: "VPSRLD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VPSRLDMasked256const", argLength: 2, reg: wkw, asm: "VPSRLD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VPSRLDMasked512const", argLength: 2, reg: wkw, asm: "VPSRLD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VPSRLQMasked128const", argLength: 2, reg: wkw, asm: "VPSRLQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VPSRLQMasked256const", argLength: 2, reg: wkw, asm: "VPSRLQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VPSRLQMasked512const", argLength: 2, reg: wkw, asm: "VPSRLQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VPSRAWMasked128const", argLength: 2, reg: wkw, asm: "VPSRAW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VPSRAWMasked256const", argLength: 2, reg: wkw, asm: "VPSRAW", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VPSRAWMasked512const", argLength: 2, reg: wkw, asm: "VPSRAW", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VPSRADMasked128const", argLength: 2, reg: wkw, asm: "VPSRAD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VPSRADMasked256const", argLength: 2, reg: wkw, asm: "VPSRAD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VPSRADMasked512const", argLength: 2, reg: wkw, asm: "VPSRAD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VPSRAQMasked128const", argLength: 2, reg: wkw, asm: "VPSRAQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VPSRAQMasked256const", argLength: 2, reg: wkw, asm: "VPSRAQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VPSRAQMasked512const", argLength: 2, reg: wkw, asm: "VPSRAQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
}
|
||||
}
|
||||
|
||||
@@ -2221,6 +2221,60 @@ const (
|
||||
OpAMD64VPSHRDQMasked128
|
||||
OpAMD64VPSHRDQMasked256
|
||||
OpAMD64VPSHRDQMasked512
|
||||
OpAMD64VPSLLW128const
|
||||
OpAMD64VPSLLW256const
|
||||
OpAMD64VPSLLW512const
|
||||
OpAMD64VPSLLD128const
|
||||
OpAMD64VPSLLD256const
|
||||
OpAMD64VPSLLD512const
|
||||
OpAMD64VPSLLQ128const
|
||||
OpAMD64VPSLLQ256const
|
||||
OpAMD64VPSLLQ512const
|
||||
OpAMD64VPSLLWMasked128const
|
||||
OpAMD64VPSLLWMasked256const
|
||||
OpAMD64VPSLLWMasked512const
|
||||
OpAMD64VPSLLDMasked128const
|
||||
OpAMD64VPSLLDMasked256const
|
||||
OpAMD64VPSLLDMasked512const
|
||||
OpAMD64VPSLLQMasked128const
|
||||
OpAMD64VPSLLQMasked256const
|
||||
OpAMD64VPSLLQMasked512const
|
||||
OpAMD64VPSRLW128const
|
||||
OpAMD64VPSRLW256const
|
||||
OpAMD64VPSRLW512const
|
||||
OpAMD64VPSRLD128const
|
||||
OpAMD64VPSRLD256const
|
||||
OpAMD64VPSRLD512const
|
||||
OpAMD64VPSRLQ128const
|
||||
OpAMD64VPSRLQ256const
|
||||
OpAMD64VPSRLQ512const
|
||||
OpAMD64VPSRAW128const
|
||||
OpAMD64VPSRAW256const
|
||||
OpAMD64VPSRAW512const
|
||||
OpAMD64VPSRAD128const
|
||||
OpAMD64VPSRAD256const
|
||||
OpAMD64VPSRAD512const
|
||||
OpAMD64VPSRAQ128const
|
||||
OpAMD64VPSRAQ256const
|
||||
OpAMD64VPSRAQ512const
|
||||
OpAMD64VPSRLWMasked128const
|
||||
OpAMD64VPSRLWMasked256const
|
||||
OpAMD64VPSRLWMasked512const
|
||||
OpAMD64VPSRLDMasked128const
|
||||
OpAMD64VPSRLDMasked256const
|
||||
OpAMD64VPSRLDMasked512const
|
||||
OpAMD64VPSRLQMasked128const
|
||||
OpAMD64VPSRLQMasked256const
|
||||
OpAMD64VPSRLQMasked512const
|
||||
OpAMD64VPSRAWMasked128const
|
||||
OpAMD64VPSRAWMasked256const
|
||||
OpAMD64VPSRAWMasked512const
|
||||
OpAMD64VPSRADMasked128const
|
||||
OpAMD64VPSRADMasked256const
|
||||
OpAMD64VPSRADMasked512const
|
||||
OpAMD64VPSRAQMasked128const
|
||||
OpAMD64VPSRAQMasked256const
|
||||
OpAMD64VPSRAQMasked512const
|
||||
|
||||
OpARMADD
|
||||
OpARMADDconst
|
||||
@@ -34317,6 +34371,789 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSLLW128const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSLLW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSLLW256const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSLLW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSLLW512const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSLLW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSLLD128const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSLLD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSLLD256const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSLLD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSLLD512const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSLLD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSLLQ128const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSLLQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSLLQ256const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSLLQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSLLQ512const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSLLQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSLLWMasked128const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSLLW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSLLWMasked256const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSLLW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSLLWMasked512const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSLLW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSLLDMasked128const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSLLD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSLLDMasked256const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSLLD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSLLDMasked512const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSLLD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSLLQMasked128const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSLLQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSLLQMasked256const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSLLQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSLLQMasked512const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSLLQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRLW128const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSRLW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRLW256const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSRLW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRLW512const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSRLW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRLD128const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSRLD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRLD256const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSRLD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRLD512const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSRLD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRLQ128const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSRLQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRLQ256const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSRLQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRLQ512const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSRLQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRAW128const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSRAW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRAW256const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSRAW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRAW512const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSRAW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRAD128const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSRAD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRAD256const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSRAD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRAD512const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSRAD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRAQ128const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSRAQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRAQ256const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSRAQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRAQ512const",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AVPSRAQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 281472829161472}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRLWMasked128const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSRLW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRLWMasked256const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSRLW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRLWMasked512const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSRLW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRLDMasked128const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSRLD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRLDMasked256const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSRLD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRLDMasked512const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSRLD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRLQMasked128const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSRLQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRLQMasked256const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSRLQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRLQMasked512const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSRLQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRAWMasked128const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSRAW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRAWMasked256const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSRAW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRAWMasked512const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSRAW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRADMasked128const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSRAD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRADMasked256const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSRAD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRADMasked512const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSRAD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRAQMasked128const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSRAQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRAQMasked256const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSRAQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "VPSRAQMasked512const",
|
||||
auxType: auxInt8,
|
||||
argLen: 2,
|
||||
asm: x86.AVPSRAQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 71494644084506624}, // K1 K2 K3 K4 K5 K6 K7
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
||||
},
|
||||
},
|
||||
},
|
||||
|
||||
{
|
||||
name: "ADD",
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -206,6 +206,24 @@ func TestPairDotProdAccumulate(t *testing.T) {
|
||||
}
|
||||
}
|
||||
|
||||
var testShiftAllVal uint64 = 3
|
||||
|
||||
func TestShiftAll(t *testing.T) {
|
||||
got := make([]int32, 4)
|
||||
simd.LoadInt32x4Slice([]int32{0b11, 0b11, 0b11, 0b11}).ShiftAllLeft(2).StoreSlice(got)
|
||||
for _, v := range got {
|
||||
if v != 0b1100 {
|
||||
t.Errorf("expect 0b1100, got %b", v)
|
||||
}
|
||||
}
|
||||
simd.LoadInt32x4Slice([]int32{0b11, 0b11, 0b11, 0b11}).ShiftAllLeft(testShiftAllVal).StoreSlice(got)
|
||||
for _, v := range got {
|
||||
if v != 0b11000 {
|
||||
t.Errorf("expect 0b11000, got %b", v)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
func TestSlicesInt8(t *testing.T) {
|
||||
a := []int8{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
|
||||
17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}
|
||||
|
||||
Reference in New Issue
Block a user