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unix: add riscv_hwprobe for riscv64

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The riscv_hwprobe system call was introduced in Linux 6.4 and allows
the caller to determine a number of interesting pieces of information
about the underlying RISC-V CPUs, e.g., which extensions they support
and whether they allow fast unaligned memory accesses.  For more information
please see:

https://docs.kernel.org/riscv/hwprobe.html

We also update linux/mksysnum.go to ensure that the generated syscall constants
written to the zsysnum_linux_*.go files are always sorted by their syscall numbers
in ascending order.

Updates golang/go#61416

Change-Id: Iedb0a86adb65faac9061b9a5969ffa09eb5b303a
Reviewed-on: https://go-review.googlesource.com/c/sys/+/510795
TryBot-Result: Gopher Robot <gobot@golang.org>
Reviewed-by: Matthew Dempsky <mdempsky@google.com>
Auto-Submit: Ian Lance Taylor <iant@google.com>
Reviewed-by: Ian Lance Taylor <iant@google.com>
Run-TryBot: Ian Lance Taylor <iant@google.com>
This commit is contained in:
Mark Ryan
2023-07-18 12:41:15 +00:00
committed by Gopher Robot
parent 70f4e408de
commit 104d4017fa
7 changed files with 173 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

49
unix/linux/types.go
View File

@@ -426,6 +426,32 @@ struct my_can_bittiming_const {
__u32 brp_max;
__u32 brp_inc;
};
#if defined(__riscv)
#include <asm/hwprobe.h>
#else
// copied from /usr/include/asm/hwprobe.h
// values are not used but they need to be defined.
#define RISCV_HWPROBE_KEY_MVENDORID 0
#define RISCV_HWPROBE_KEY_MARCHID 1
#define RISCV_HWPROBE_KEY_MIMPID 2
#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3
#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0)
#define RISCV_HWPROBE_KEY_IMA_EXT_0 4
#define RISCV_HWPROBE_IMA_FD (1 << 0)
#define RISCV_HWPROBE_IMA_C (1 << 1)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
#define RISCV_HWPROBE_MISALIGNED_SLOW (2 << 0)
#define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0)
#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0)
#define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0)
struct riscv_hwprobe {};
#endif
*/
import "C"
@@ -5747,3 +5773,26 @@ const (
VIRTIO_NET_HDR_GSO_UDP_L4 = C.VIRTIO_NET_HDR_GSO_UDP_L4
VIRTIO_NET_HDR_GSO_ECN = C.VIRTIO_NET_HDR_GSO_ECN
)
type RISCVHWProbePairs C.struct_riscv_hwprobe
// Filtered out for non RISC-V architectures in mkpost.go
// generated by:
// perl -nlE '/^#define\s+(RISCV_HWPROBE_\w+)/ && say "$1 = C.$1"' /tmp/riscv64/include/asm/hwprobe.h
const (
RISCV_HWPROBE_KEY_MVENDORID = C.RISCV_HWPROBE_KEY_MVENDORID
RISCV_HWPROBE_KEY_MARCHID = C.RISCV_HWPROBE_KEY_MARCHID
RISCV_HWPROBE_KEY_MIMPID = C.RISCV_HWPROBE_KEY_MIMPID
RISCV_HWPROBE_KEY_BASE_BEHAVIOR = C.RISCV_HWPROBE_KEY_BASE_BEHAVIOR
RISCV_HWPROBE_BASE_BEHAVIOR_IMA = C.RISCV_HWPROBE_BASE_BEHAVIOR_IMA
RISCV_HWPROBE_KEY_IMA_EXT_0 = C.RISCV_HWPROBE_KEY_IMA_EXT_0
RISCV_HWPROBE_IMA_FD = C.RISCV_HWPROBE_IMA_FD
RISCV_HWPROBE_IMA_C = C.RISCV_HWPROBE_IMA_C
RISCV_HWPROBE_KEY_CPUPERF_0 = C.RISCV_HWPROBE_KEY_CPUPERF_0
RISCV_HWPROBE_MISALIGNED_UNKNOWN = C.RISCV_HWPROBE_MISALIGNED_UNKNOWN
RISCV_HWPROBE_MISALIGNED_EMULATED = C.RISCV_HWPROBE_MISALIGNED_EMULATED
RISCV_HWPROBE_MISALIGNED_SLOW = C.RISCV_HWPROBE_MISALIGNED_SLOW
RISCV_HWPROBE_MISALIGNED_FAST = C.RISCV_HWPROBE_MISALIGNED_FAST
RISCV_HWPROBE_MISALIGNED_UNSUPPORTED = C.RISCV_HWPROBE_MISALIGNED_UNSUPPORTED
RISCV_HWPROBE_MISALIGNED_MASK = C.RISCV_HWPROBE_MISALIGNED_MASK
)