cpu: add support for detecting RISC-V extensions

Add a RISCV64 variable to cpu that indicates both the presence
of RISC-V extensions and performance information about the underlying
RISC-V cores.  The variable is only populated with non false values on
Linux.  The detection code first attempts to use the riscv_hwprobe
syscall introduced in Linux 6.4, falling back to HWCAP if riscv_hwprobe
is not supported.  The patch can detect the C, V, Zba, Zbb and Zbs
extensions.  V, Zba, Zbb and Zbs can only be detected on a 6.5 kernel
or later (without backports).

Updates golang/go#61416

Change-Id: I40f92724ee3d337c06bdc559ff0b18a8f6bfda9f
Reviewed-on: https://go-review.googlesource.com/c/sys/+/605815
Reviewed-by: Cherry Mui <cherryyz@google.com>
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Joel Sing <joel@sing.id.au>
Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>

cpu/cpu.go

@@ -201,6 +201,25 @@ var S390X struct {
 	_         CacheLinePad
 }
 
+// RISCV64 contains the supported CPU features and performance characteristics for riscv64
+// platforms. The booleans in RISCV64, with the exception of HasFastMisaligned, indicate
+// the presence of RISC-V extensions.
+//
+// It is safe to assume that all the RV64G extensions are supported and so they are omitted from
+// this structure. As riscv64 Go programs require at least RV64G, the code that populates
+// this structure cannot run successfully if some of the RV64G extensions are missing.
+// The struct is padded to avoid false sharing.
+var RISCV64 struct {
+	_                 CacheLinePad
+	HasFastMisaligned bool // Fast misaligned accesses
+	HasC              bool // Compressed instruction-set extension
+	HasV              bool // Vector extension compatible with RVV 1.0
+	HasZba            bool // Address generation instructions extension
+	HasZbb            bool // Basic bit-manipulation extension
+	HasZbs            bool // Single-bit instructions extension
+	_                 CacheLinePad
+}
+
 func init() {
 	archInit()
 	initOptions()