From 3675c4cc48d381cf54212e0aea81448a272d7c01 Mon Sep 17 00:00:00 2001 From: Tobias Klauser Date: Thu, 10 Oct 2024 09:54:41 +0200 Subject: [PATCH] cpu: use MRS instruction to read arm64 system registers Use the MRS instruction with the corresponding system register instead of encoding the instructions using a WORD directive. Change-Id: I2995dfa6ad731cb03867160127db84898adfdda5 Reviewed-on: https://go-review.googlesource.com/c/sys/+/583135 LUCI-TryBot-Result: Go LUCI Reviewed-by: Michael Knyszek Reviewed-by: David Chase Auto-Submit: Tobias Klauser --- cpu/cpu_arm64.s | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/cpu/cpu_arm64.s b/cpu/cpu_arm64.s index 9053a43e..601a5f7e 100644 --- a/cpu/cpu_arm64.s +++ b/cpu/cpu_arm64.s @@ -9,16 +9,14 @@ // func getisar0() uint64 TEXT ·getisar0(SB),NOSPLIT,$0-8 // get Instruction Set Attributes 0 into x0 - // mrs x0, ID_AA64ISAR0_EL1 = d5380600 - WORD $0xd5380600 + MRS ID_AA64ISAR0_EL1, R0 MOVD R0, ret+0(FP) RET // func getisar1() uint64 TEXT ·getisar1(SB),NOSPLIT,$0-8 // get Instruction Set Attributes 1 into x0 - // mrs x0, ID_AA64ISAR1_EL1 = d5380620 - WORD $0xd5380620 + MRS ID_AA64ISAR1_EL1, R0 MOVD R0, ret+0(FP) RET @@ -33,15 +31,13 @@ TEXT ·getmmfr1(SB),NOSPLIT,$0-8 // func getpfr0() uint64 TEXT ·getpfr0(SB),NOSPLIT,$0-8 // get Processor Feature Register 0 into x0 - // mrs x0, ID_AA64PFR0_EL1 = d5380400 - WORD $0xd5380400 + MRS ID_AA64PFR0_EL1, R0 MOVD R0, ret+0(FP) RET // func getzfr0() uint64 TEXT ·getzfr0(SB),NOSPLIT,$0-8 // get SVE Feature Register 0 into x0 - // mrs x0, ID_AA64ZFR0_EL1 = d5380480 - WORD $0xd5380480 + MRS ID_AA64ZFR0_EL1, R0 MOVD R0, ret+0(FP) RET