From 4f4f1c6feacd5e05a726e4fd415d0462cab0bebb Mon Sep 17 00:00:00 2001 From: Cherry Mui Date: Mon, 24 Nov 2025 14:54:30 -0800 Subject: [PATCH] Revert "cpu: add HPDS, LOR, PAN detection for arm64" This reverts CL 704075. Reason for revert: Based on golang/go#76386, it doesn't seem to work correctly. Fixes golang/go#76386. Change-Id: I51ccbc8715c25c0d061d56dfbf0e8158f1207018 Reviewed-on: https://go-review.googlesource.com/c/sys/+/724160 LUCI-TryBot-Result: Go LUCI Reviewed-by: Michael Knyszek Auto-Submit: Cherry Mui --- cpu/cpu.go | 3 --- cpu/cpu_arm64.go | 20 ++------------------ cpu/cpu_arm64.s | 7 ------- cpu/cpu_gc_arm64.go | 1 - cpu/cpu_gccgo_arm64.go | 1 - cpu/cpu_netbsd_arm64.go | 2 +- cpu/cpu_openbsd_arm64.go | 2 +- 7 files changed, 4 insertions(+), 32 deletions(-) diff --git a/cpu/cpu.go b/cpu/cpu.go index 34c9ae76..63541994 100644 --- a/cpu/cpu.go +++ b/cpu/cpu.go @@ -92,9 +92,6 @@ var ARM64 struct { HasSHA2 bool // SHA2 hardware implementation HasCRC32 bool // CRC32 hardware implementation HasATOMICS bool // Atomic memory operation instruction set - HasHPDS bool // Hierarchical permission disables in translations tables - HasLOR bool // Limited ordering regions - HasPAN bool // Privileged access never HasFPHP bool // Half precision floating-point instruction set HasASIMDHP bool // Advanced SIMD half precision instruction set HasCPUID bool // CPUID identification scheme registers diff --git a/cpu/cpu_arm64.go b/cpu/cpu_arm64.go index f449c679..af2aa99f 100644 --- a/cpu/cpu_arm64.go +++ b/cpu/cpu_arm64.go @@ -65,10 +65,10 @@ func setMinimalFeatures() { func readARM64Registers() { Initialized = true - parseARM64SystemRegisters(getisar0(), getisar1(), getmmfr1(), getpfr0()) + parseARM64SystemRegisters(getisar0(), getisar1(), getpfr0()) } -func parseARM64SystemRegisters(isar0, isar1, mmfr1, pfr0 uint64) { +func parseARM64SystemRegisters(isar0, isar1, pfr0 uint64) { // ID_AA64ISAR0_EL1 switch extractBits(isar0, 4, 7) { case 1: @@ -152,22 +152,6 @@ func parseARM64SystemRegisters(isar0, isar1, mmfr1, pfr0 uint64) { ARM64.HasI8MM = true } - // ID_AA64MMFR1_EL1 - switch extractBits(mmfr1, 12, 15) { - case 1, 2: - ARM64.HasHPDS = true - } - - switch extractBits(mmfr1, 16, 19) { - case 1: - ARM64.HasLOR = true - } - - switch extractBits(mmfr1, 20, 23) { - case 1, 2, 3: - ARM64.HasPAN = true - } - // ID_AA64PFR0_EL1 switch extractBits(pfr0, 16, 19) { case 0: diff --git a/cpu/cpu_arm64.s b/cpu/cpu_arm64.s index a4f24b3b..3b0450a0 100644 --- a/cpu/cpu_arm64.s +++ b/cpu/cpu_arm64.s @@ -20,13 +20,6 @@ TEXT ·getisar1(SB),NOSPLIT,$0-8 MOVD R0, ret+0(FP) RET -// func getmmfr1() uint64 -TEXT ·getmmfr1(SB),NOSPLIT,$0-8 - // get Memory Model Feature Register 1 into x0 - MRS ID_AA64MMFR1_EL1, R0 - MOVD R0, ret+0(FP) - RET - // func getpfr0() uint64 TEXT ·getpfr0(SB),NOSPLIT,$0-8 // get Processor Feature Register 0 into x0 diff --git a/cpu/cpu_gc_arm64.go b/cpu/cpu_gc_arm64.go index e3fc5a8d..6ac6e1ef 100644 --- a/cpu/cpu_gc_arm64.go +++ b/cpu/cpu_gc_arm64.go @@ -8,6 +8,5 @@ package cpu func getisar0() uint64 func getisar1() uint64 -func getmmfr1() uint64 func getpfr0() uint64 func getzfr0() uint64 diff --git a/cpu/cpu_gccgo_arm64.go b/cpu/cpu_gccgo_arm64.go index 8df2079e..7f194678 100644 --- a/cpu/cpu_gccgo_arm64.go +++ b/cpu/cpu_gccgo_arm64.go @@ -8,5 +8,4 @@ package cpu func getisar0() uint64 { return 0 } func getisar1() uint64 { return 0 } -func getmmfr1() uint64 { return 0 } func getpfr0() uint64 { return 0 } diff --git a/cpu/cpu_netbsd_arm64.go b/cpu/cpu_netbsd_arm64.go index 19aea063..ebfb3fc8 100644 --- a/cpu/cpu_netbsd_arm64.go +++ b/cpu/cpu_netbsd_arm64.go @@ -167,7 +167,7 @@ func doinit() { setMinimalFeatures() return } - parseARM64SystemRegisters(cpuid.aa64isar0, cpuid.aa64isar1, cpuid.aa64mmfr1, cpuid.aa64pfr0) + parseARM64SystemRegisters(cpuid.aa64isar0, cpuid.aa64isar1, cpuid.aa64pfr0) Initialized = true } diff --git a/cpu/cpu_openbsd_arm64.go b/cpu/cpu_openbsd_arm64.go index 87fd3a77..85b64d5c 100644 --- a/cpu/cpu_openbsd_arm64.go +++ b/cpu/cpu_openbsd_arm64.go @@ -59,7 +59,7 @@ func doinit() { if !ok { return } - parseARM64SystemRegisters(isar0, isar1, 0, 0) + parseARM64SystemRegisters(isar0, isar1, 0) Initialized = true }