From 538ab54ba952cc4c7c705fa213fbf7993c97c175 Mon Sep 17 00:00:00 2001 From: Tobias Klauser Date: Mon, 7 May 2018 11:54:54 +0200 Subject: [PATCH] cpu: introduce and export type CacheLinePad Add a CacheLinePad struct type that has a size of cacheLineSize. This can be used for padding structs in order to avoid false sharing. Fixes golang/go#25203 Change-Id: I6b6daf91ea0e9c50428ffa053035429c3921b461 Reviewed-on: https://go-review.googlesource.com/111775 Run-TryBot: Tobias Klauser TryBot-Result: Gobot Gobot Reviewed-by: Brad Fitzpatrick --- cpu/cpu.go | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/cpu/cpu.go b/cpu/cpu.go index 2d1fc12f..3d88f866 100644 --- a/cpu/cpu.go +++ b/cpu/cpu.go @@ -6,6 +6,9 @@ // various CPU architectures. package cpu +// CacheLinePad is used to pad structs to avoid false sharing. +type CacheLinePad struct{ _ [cacheLineSize]byte } + // X86 contains the supported CPU features of the // current X86/AMD64 platform. If the current platform // is not X86/AMD64 then all feature flags are false. @@ -14,7 +17,7 @@ package cpu // and HasAVX2 are only set if the OS supports XMM and YMM // registers in addition to the CPUID feature bit being set. var X86 struct { - _ [cacheLineSize]byte + _ CacheLinePad HasAES bool // AES hardware implementation (AES NI) HasADX bool // Multi-precision add-carry instruction extensions HasAVX bool // Advanced vector extension @@ -31,5 +34,5 @@ var X86 struct { HasSSSE3 bool // Supplemental streaming SIMD extension 3 HasSSE41 bool // Streaming SIMD extension 4 and 4.1 HasSSE42 bool // Streaming SIMD extension 4 and 4.2 - _ [cacheLineSize]byte + _ CacheLinePad }