From 6239615695530c23a1927a4c02a1e8a401b79c94 Mon Sep 17 00:00:00 2001 From: Chongyi Zheng Date: Tue, 28 Oct 2025 01:51:46 +0000 Subject: [PATCH] cpu: add HPDS, LOR, PAN detection for arm64 This CL gets ID_AA64MMFR1_EL1, Memory Model Feature Register 1, and grabs HPDS, LOR, PAN features from its bits. Fixes golang/go#75472. Change-Id: Ic04b109d79aceba9b3b1d3a1ea514fcf132007c5 GitHub-Last-Rev: f938ff468bca49cc7863aa26e7a880eec2823bb4 GitHub-Pull-Request: golang/sys#263 Reviewed-on: https://go-review.googlesource.com/c/sys/+/704075 Reviewed-by: Keith Randall Auto-Submit: Keith Randall Reviewed-by: Michael Knyszek LUCI-TryBot-Result: Go LUCI Reviewed-by: Keith Randall --- cpu/cpu.go | 3 +++ cpu/cpu_arm64.go | 20 ++++++++++++++++++-- cpu/cpu_arm64.s | 8 ++++++++ cpu/cpu_gc_arm64.go | 1 + cpu/cpu_gccgo_arm64.go | 1 + cpu/cpu_netbsd_arm64.go | 2 +- cpu/cpu_openbsd_arm64.go | 2 +- 7 files changed, 33 insertions(+), 4 deletions(-) diff --git a/cpu/cpu.go b/cpu/cpu.go index 63541994..34c9ae76 100644 --- a/cpu/cpu.go +++ b/cpu/cpu.go @@ -92,6 +92,9 @@ var ARM64 struct { HasSHA2 bool // SHA2 hardware implementation HasCRC32 bool // CRC32 hardware implementation HasATOMICS bool // Atomic memory operation instruction set + HasHPDS bool // Hierarchical permission disables in translations tables + HasLOR bool // Limited ordering regions + HasPAN bool // Privileged access never HasFPHP bool // Half precision floating-point instruction set HasASIMDHP bool // Advanced SIMD half precision instruction set HasCPUID bool // CPUID identification scheme registers diff --git a/cpu/cpu_arm64.go b/cpu/cpu_arm64.go index af2aa99f..f449c679 100644 --- a/cpu/cpu_arm64.go +++ b/cpu/cpu_arm64.go @@ -65,10 +65,10 @@ func setMinimalFeatures() { func readARM64Registers() { Initialized = true - parseARM64SystemRegisters(getisar0(), getisar1(), getpfr0()) + parseARM64SystemRegisters(getisar0(), getisar1(), getmmfr1(), getpfr0()) } -func parseARM64SystemRegisters(isar0, isar1, pfr0 uint64) { +func parseARM64SystemRegisters(isar0, isar1, mmfr1, pfr0 uint64) { // ID_AA64ISAR0_EL1 switch extractBits(isar0, 4, 7) { case 1: @@ -152,6 +152,22 @@ func parseARM64SystemRegisters(isar0, isar1, pfr0 uint64) { ARM64.HasI8MM = true } + // ID_AA64MMFR1_EL1 + switch extractBits(mmfr1, 12, 15) { + case 1, 2: + ARM64.HasHPDS = true + } + + switch extractBits(mmfr1, 16, 19) { + case 1: + ARM64.HasLOR = true + } + + switch extractBits(mmfr1, 20, 23) { + case 1, 2, 3: + ARM64.HasPAN = true + } + // ID_AA64PFR0_EL1 switch extractBits(pfr0, 16, 19) { case 0: diff --git a/cpu/cpu_arm64.s b/cpu/cpu_arm64.s index 22cc9984..9053a43e 100644 --- a/cpu/cpu_arm64.s +++ b/cpu/cpu_arm64.s @@ -22,6 +22,14 @@ TEXT ·getisar1(SB),NOSPLIT,$0-8 MOVD R0, ret+0(FP) RET +// func getmmfr1() uint64 +TEXT ·getmmfr1(SB),NOSPLIT,$0-8 + // get Memory Model Feature Register 1 into x0 + // mrs x0, ID_AA64MMFR1_EL1 = d5380720 + WORD $0xd5380720 + MOVD R0, ret+0(FP) + RET + // func getpfr0() uint64 TEXT ·getpfr0(SB),NOSPLIT,$0-8 // get Processor Feature Register 0 into x0 diff --git a/cpu/cpu_gc_arm64.go b/cpu/cpu_gc_arm64.go index 6ac6e1ef..e3fc5a8d 100644 --- a/cpu/cpu_gc_arm64.go +++ b/cpu/cpu_gc_arm64.go @@ -8,5 +8,6 @@ package cpu func getisar0() uint64 func getisar1() uint64 +func getmmfr1() uint64 func getpfr0() uint64 func getzfr0() uint64 diff --git a/cpu/cpu_gccgo_arm64.go b/cpu/cpu_gccgo_arm64.go index 7f194678..8df2079e 100644 --- a/cpu/cpu_gccgo_arm64.go +++ b/cpu/cpu_gccgo_arm64.go @@ -8,4 +8,5 @@ package cpu func getisar0() uint64 { return 0 } func getisar1() uint64 { return 0 } +func getmmfr1() uint64 { return 0 } func getpfr0() uint64 { return 0 } diff --git a/cpu/cpu_netbsd_arm64.go b/cpu/cpu_netbsd_arm64.go index ebfb3fc8..19aea063 100644 --- a/cpu/cpu_netbsd_arm64.go +++ b/cpu/cpu_netbsd_arm64.go @@ -167,7 +167,7 @@ func doinit() { setMinimalFeatures() return } - parseARM64SystemRegisters(cpuid.aa64isar0, cpuid.aa64isar1, cpuid.aa64pfr0) + parseARM64SystemRegisters(cpuid.aa64isar0, cpuid.aa64isar1, cpuid.aa64mmfr1, cpuid.aa64pfr0) Initialized = true } diff --git a/cpu/cpu_openbsd_arm64.go b/cpu/cpu_openbsd_arm64.go index 85b64d5c..87fd3a77 100644 --- a/cpu/cpu_openbsd_arm64.go +++ b/cpu/cpu_openbsd_arm64.go @@ -59,7 +59,7 @@ func doinit() { if !ok { return } - parseARM64SystemRegisters(isar0, isar1, 0) + parseARM64SystemRegisters(isar0, isar1, 0, 0) Initialized = true }