Files
sys/cpu/cpu_arm64.s
Chongyi Zheng f938ff468b cpu: add HPDS, LOR, PAN detection for arm64
This CL gets ID_AA64MMFR1_EL1, Memory Model Feature Register 1, and
grabs HPDS, LOR, PAN features from its bits.

Fixes golang/go#75472.
2025-10-27 20:49:42 -05:00

48 lines
1.1 KiB
ArmAsm

// Copyright 2019 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
//go:build gc
#include "textflag.h"
// func getisar0() uint64
TEXT ·getisar0(SB),NOSPLIT,$0-8
// get Instruction Set Attributes 0 into x0
// mrs x0, ID_AA64ISAR0_EL1 = d5380600
WORD $0xd5380600
MOVD R0, ret+0(FP)
RET
// func getisar1() uint64
TEXT ·getisar1(SB),NOSPLIT,$0-8
// get Instruction Set Attributes 1 into x0
// mrs x0, ID_AA64ISAR1_EL1 = d5380620
WORD $0xd5380620
MOVD R0, ret+0(FP)
RET
// func getmmfr1() uint64
TEXT ·getmmfr1(SB),NOSPLIT,$0-8
// get Memory Model Feature Register 1 into x0
// mrs x0, ID_AA64MMFR1_EL1 = d5380720
WORD $0xd5380720
MOVD R0, ret+0(FP)
RET
// func getpfr0() uint64
TEXT ·getpfr0(SB),NOSPLIT,$0-8
// get Processor Feature Register 0 into x0
// mrs x0, ID_AA64PFR0_EL1 = d5380400
WORD $0xd5380400
MOVD R0, ret+0(FP)
RET
// func getzfr0() uint64
TEXT ·getzfr0(SB),NOSPLIT,$0-8
// get SVE Feature Register 0 into x0
// mrs x0, ID_AA64ZFR0_EL1 = d5380480
WORD $0xd5380480
MOVD R0, ret+0(FP)
RET