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cpu: add HPDS, LOR, PAN detection for arm64

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This CL gets ID_AA64MMFR1_EL1, Memory Model Feature Register 1, and
grabs HPDS, LOR, PAN features from its bits.

Fixes golang/go#75472.
This commit is contained in:
Chongyi Zheng
2025-09-15 21:55:11 -05:00
parent 28c5bda5d4
commit f938ff468b
7 changed files with 33 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
cpu/cpu.go
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@@ -92,6 +92,9 @@ var ARM64 struct {
HasSHA2 bool // SHA2 hardware implementation
HasCRC32 bool // CRC32 hardware implementation
HasATOMICS bool // Atomic memory operation instruction set
HasHPDS bool // Hierarchical permission disables in translations tables
HasLOR bool // Limited ordering regions
HasPAN bool // Privileged access never
HasFPHP bool // Half precision floating-point instruction set
HasASIMDHP bool // Advanced SIMD half precision instruction set
HasCPUID bool // CPUID identification scheme registers

20
cpu/cpu_arm64.go
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@@ -65,10 +65,10 @@ func setMinimalFeatures() {
func readARM64Registers() {
Initialized = true
parseARM64SystemRegisters(getisar0(), getisar1(), getpfr0())
parseARM64SystemRegisters(getisar0(), getisar1(), getmmfr1(), getpfr0())
}
func parseARM64SystemRegisters(isar0, isar1, pfr0 uint64) {
func parseARM64SystemRegisters(isar0, isar1, mmfr1, pfr0 uint64) {
// ID_AA64ISAR0_EL1
switch extractBits(isar0, 4, 7) {
case 1:
@@ -152,6 +152,22 @@ func parseARM64SystemRegisters(isar0, isar1, pfr0 uint64) {
ARM64.HasI8MM = true
}
// ID_AA64MMFR1_EL1
switch extractBits(mmfr1, 12, 15) {
case 1, 2:
ARM64.HasHPDS = true
}
switch extractBits(mmfr1, 16, 19) {
case 1:
ARM64.HasLOR = true
}
switch extractBits(mmfr1, 20, 23) {
case 1, 2, 3:
ARM64.HasPAN = true
}
// ID_AA64PFR0_EL1
switch extractBits(pfr0, 16, 19) {
case 0:

8
cpu/cpu_arm64.s
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@@ -22,6 +22,14 @@ TEXT ·getisar1(SB),NOSPLIT,$0-8
MOVD R0, ret+0(FP)
RET
// func getmmfr1() uint64
TEXT ·getmmfr1(SB),NOSPLIT,$0-8
// get Memory Model Feature Register 1 into x0
// mrs x0, ID_AA64MMFR1_EL1 = d5380720
WORD $0xd5380720
MOVD R0, ret+0(FP)
RET
// func getpfr0() uint64
TEXT ·getpfr0(SB),NOSPLIT,$0-8
// get Processor Feature Register 0 into x0

1
cpu/cpu_gc_arm64.go
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@@ -8,5 +8,6 @@ package cpu
func getisar0() uint64
func getisar1() uint64
func getmmfr1() uint64
func getpfr0() uint64
func getzfr0() uint64

1
cpu/cpu_gccgo_arm64.go
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@@ -8,4 +8,5 @@ package cpu
func getisar0() uint64 { return 0 }
func getisar1() uint64 { return 0 }
func getmmfr1() uint64 { return 0 }
func getpfr0() uint64 { return 0 }

2
cpu/cpu_netbsd_arm64.go
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@@ -167,7 +167,7 @@ func doinit() {
setMinimalFeatures()
return
}
parseARM64SystemRegisters(cpuid.aa64isar0, cpuid.aa64isar1, cpuid.aa64pfr0)
parseARM64SystemRegisters(cpuid.aa64isar0, cpuid.aa64isar1, cpuid.aa64mmfr1, cpuid.aa64pfr0)
Initialized = true
}

2
cpu/cpu_openbsd_arm64.go
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@@ -59,7 +59,7 @@ func doinit() {
if !ok {
return
}
parseARM64SystemRegisters(isar0, isar1, 0)
parseARM64SystemRegisters(isar0, isar1, 0, 0)
Initialized = true
}